1. Field of the Invention
The present invention relates generally to phase and frequency control. More particularly, it relates to a method and apparatus for controlling phase and frequency using an oscillator in combination with a phase selector within a digitally controlled phase-locked loop.
2. Description of Related Art
Typically, read channel integrated circuits associated with data storage devices, such as magnetic hard disk drives, have two modes of operation for controlling the system clock: a write mode having a write loop and a read mode having a read loop. In the write loop, the system clock is synthesized from an external reference clock, such as the output of a crystal oscillator. The synthesized frequency is typically a rational multiple, N/D (where N and D are integers), of the reference clock. Frequency synthesis is a well known technique in the art. In the write loop of the timing control loop, specified data is obtained and written to a magnetic medium at this synthesized frequency, one binary bit of data per cycle. Furthermore, in such loop, phase errors are typically measured by a phase-frequency detector (PFD).
In the second loop of operation for controlling the system clock, the read loop, data is read from the magnetic medium at the same rate it was written. In the read loop, the system clock is aligned in phase and frequency to the data stream read from the magnetic medium. Typically, the continuous time signals from the magnetic medium are captured by a sample and hold circuit (S/H) timed by the system clock. The phase and frequency of the system clock are controlled by such discrete samples through the feedback control in the read loop. Furthermore, the read loop timing itself has two modes of operation, acquisition and tracking. The acquisition mode occurs prior to the reading of actual data and is characterized by high gain and wide band to rapidly synchronize to the phase of the incoming data stream. The tracking mode must also have wide bandwidth but gain is normally reduced to avoid spurious phase disturbances.
Using known techniques (Sidiropoulos et al., xe2x80x9cA Semi Digital Delay-Locked Loopxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, November 1997) 2N phase outputs of an N stage delay-locked loop (DLL) can be used to produce one phase output interpolated between any two adjacent phases from among the 2N phases. Sidiropoulos et al. show a scheme for digitally changing phase in increments of 27xcfx80/192 with a phase range of 2xcfx80 radians by utilizing a delay line. The Sidiropoulos scheme requires both ends of such delay line to be phase aligned to the reference clock, thus requiring a separate control loop. In Sidiropoulos, a 6 stage delay line produces phase steps of 2xcfx80/12 radians, or coarse 30 degree phase steps, and a phase interpolator produces 16 fine steps for each of the 12 coarse steps. Furthermore, a phase detector and charge pump are used to accomplish the phase locking in the Sidiropoulos scheme.
Generally, since the read and write control loops are not active simultaneously, common elements may be shared between the two control loops. Such common elements include, for example, a Current Controlled Oscillator (ICO), a Voltage Controlled Oscillator (VCO), a filter capacitor, a Voltage to Current (V to I) circuit, Charge Pumps, and the like.
In a phase-locked loop (PLL) phase is typically controlled by a filter having a resistor in series with a capacitor to produce a filter having one pole. However, since integrated circuits typically do not have linear resistive elements adequate for producing resistor elements for filters, a Proportional-Integral-Derivative (PID) Control may alternatively be used to control phase. Generally, integrated circuits employ a Proportional-Integral (PI) control by having two signal paths, one called a proportional path and one called an integral path. The proportional path has a gain, Kp, independent of frequency. The integral path has gain, KI/s, where s is the LaPlace variable. Therein, the sum of the proportional and integral path is Kp+KI/s. As such, the PI signals mimic the resistor in series with a capacitor of a filter having Kp/KI pole.
Generally, the prior art discloses indirectly controlling phase by controlling frequency of an oscillator. Such phase controllers typically control phase by controlling frequency. However, in a digitally controlled phase locked loop, the gain of the closed loop varies with operating frequency, and thus controlling phase indirectly by controlling the frequency is not optimum. Therefore, improvements are needed in controlling phase in a digitally controlled PLL, as well as controlling phase and frequency independently of each other. Additionally, further improvements are needed in selecting and outputting a fine phase in the read loop for rapid acquisition in such read loop by adapting phase to data quickly within a PLL.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved apparatus and method for controlling phase within a phase locked loop. Another object of the present invention is to provide an improved apparatus and method for outputting a fine phase in a read phase locked loop. Yet another object of the present invention is to provide an improved method and apparatus for decreasing the time required to achieve phase acquisition within a phase locked loop.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of controlling a variable phase in a phase locked loop. Preferably, the variable phase is controlled by providing an oscillator having a plurality of phases, wherein such plurality of phases have a first and second phase, providing a phase selector, inputting the first and second phases from the oscillator into the phase selector, and subsequently controlling the variable phase within a phase locked loop. In controlling the variable phase within the phase locked loop, the phase selector selects a desired phase among the variable phase between the first and second phases, thereafter such phase selector outputs the selected phase thereby controlling the variable phase within the phase locked loop. The oscillator of the present invention may comprise a single loop architecture.
The present embodiment of the invention may further comprise providing a timing signal, outputting the timing signal to a proportion-integral controller thereby generating a oscillator control signal, and outputting the oscillator control signal to the oscillator wherein the first and second phases employ the oscillator control signal generated by the timing signal to represent a timing error. In the present invention, such timing error may comprise a digital timing error.
Preferably, the oscillator of the present method of controlling a variable phase in a phase locked loop is a current controlled oscillator (ICO). In a preferred embodiment of the present invention, the oscillator has a frequency which is controlled by inputting a frequency input control into the oscillator. Wherein such frequency input control comprises proportional control, integral control or differential control. A preferred embodiment of the present invention may further include a first multiplexer having a digital control for selecting the first phase and a second multiplexer having a digital control for selecting the second phase. Furthermore, such first and second multiplexers having digital controls, the digital controls selecting one of the plurality of phases from the oscillator.
Preferably in the present invention, the first and second phases selected from the oscillator are adjacent phases within such oscillator.
In another preferred embodiment of the present invention the phase selector comprises a finite state machine, at least two multiplexers and a phase interpolator. In various embodiments of the present embodiment, the phase selector may have applied to it proportional control, integral control, differential control, and combinations thereof.
A preferred embodiment of the present invention may further comprise a write loop aligned to a reference clock and a read loop aligned to a continuous timing data signal, wherein the oscillator exists within both the write and read loops while the phase selector exists within the read loop. Furthermore, the write loop may be inactive while the read loop is active, therein the read loop acquiring timing data from a continuous timing data signal and a proportional controller in the read loop producing proportional control to the phase selector. Such an embodiment may further comprise a common integral control signal providing integral control to the oscillator, thereby producing proportional, integral, or differential control in the read loop to control phase of both the oscillator and phase selector.
Alternatively, the write and read loops may be simultaneously active, wherein the write loop is phase aligned to a reference clock while the read loop is phase aligned to the continuous timing data signal, thereby producing proportional, integral, or differential control in the write loop while simultaneously producing proportional, integral, or differential control in the read loop.
Preferably, the oscillator comprises N oscillator stages having 2N phase outputs wherein the phase selector comprises a digitally controlled fine interpolator having 12 states for interpolating phase between the first and second phases in equally spaced increments comprising 2xcfx80/96 radians.
The phase interpolator may comprise first and second current weighted delays which are substantially inversely proportional to a control current wherein the phase interpolator inputs the first phase into the first delay stage while inputting the second phase into the second delay stage. Such first and second delay stages share a total current such that the digital control input causes a fraction F of the current I to flow to the control input of the first delay stage and a fraction (1xe2x88x92F) of the current I to flow to the control input of the second delay stage.
In another aspect, the present invention provides a phase locked loop for controlling a variable phase comprising an oscillator adapted to provide a plurality of phase outputs, a phase selector, a first and second phase outputs selected from the oscillator adapted to provide a plurality of phase outputs, and a phase locked loop. Such phase locked loop comprises the oscillator, phase selector, and first and second phase outputs, wherein the phase selector is adapted to output a desired variable phase selected among a variable phase between the first and second phase outputs from the oscillator, thereby the phase locked loop is adapted to control the variable phase. Preferably, the oscillator comprises a single loop architecture.
The above embodiment of the present invention may further comprise a timing signal, a proportional-integral controller adapted to generate from the timing signal an oscillator control signal; and a frequency generated by the oscillator, wherein the first and second phases of the oscillator are adapted to employ the oscillator control signal to generate the timing error. In the present invention, such timing error may comprise a digital timing error.
Such an embodiment of the present invention may further comprise a first multiplexer having a digital control adapted to select the first phase and a second multiplexer having a digital control adapted to select the second phase. The digital controls are adapted to select one of the plurality of phases from the oscillator.
Preferably, the phase selector comprises a finite state machine, at least two multiplexers and a phase interpolator.
The present embodiment may further comprise a write loop aligned to a reference clock and a read loop aligned to a continuous timing data signal, wherein the oscillator exists within both the write and read loops while the phase selector exists within the read loop.
Preferably, the oscillator comprises N oscillator stages having 2N phase outputs while the phase selector comprises a digitally controlled fine interpolator having 12 states for interpolating phase between the first and second phases in equally spaced increments comprising 2xcfx80/96 radians.